Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process
UMC 0.13um LL FSG Logic process high density POWERSLASH Core Cell Library.
- UMC
- 130nm
- LL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process
UMC 0.13um LL FSG Logic process high density POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process FSC0H_J POWERSLASHKit core Library.
Standard Cell PowerSlash(TM) Library IP, UMC 0.13um SP/FSG process
UMC 0.13um SP FSG Logic process high density POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/LL process
UMC 0.11um eFlash/LL process 8-Track Cell Library.
Standard Cell PowerSlash(TM) Library IP, UMC 0.11um LL/FSG process
UMC 0.11um LL/FSG Logic process high density POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, 7 tracks, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process high density POWERSLASH (POWERSLASH) Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, 8 tracks, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash/HS process 8-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K Logic process UHS Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm eHV process
UMC 55nm HV/HVT Low-K Logic process high speed Standard Core Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Logic process 7-Track Mini Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 7-Track Mini-Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 7-Track Generic Core Cell Library.