General Purpose IO IP, 3.3V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process 3.3V tolerance standard IO Cell Library.
- UMC
- 250nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
General Purpose IO IP, 3.3V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process 3.3V tolerance standard IO Cell Library.
General Purpose IO IP, UMC 0.18um LL process
UMC 0.18um LL Logic process true 3.3V standard IO Cell Library.
General Purpose IO IP, 5V input tolerance, UMC 0.18um LL process
UMC 0.18um LL Logic process 5V tolerance standard IO Cell Library.
General Purpose IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 3.3V standard IO Cell Library.
General Purpose IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 1.8V standard IO Cell Library.
General Purpose IO IP, 5V input tolerance, UMC 0.18um G2 process
UMC 0.18um GII Logic process 5V tolerance standard IO Cell Library.
General Purpose IO IP, UMC 0.13um process
UMC 0.13um ture 3.3V Generic IO IP.
General Purpose IO IP, 5V tolerance, UMC 0.13um process
UMC 0.13um 5V tolerance gengric IO.
General Purpose IO IP, SD3.0 I/O, Support built-in Pull-Up / Pull-Down , UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 1.8V BOAC EMMC IO Cell Library (with customized PU/PD function).
Dual Port SRAM Compiler IP, UMC 90nm SP process
UMC 90nm SP/RVT/ Low-K process synchronous Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process with row Redundancy Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 55nm eHV process
UMC 55nm eHV process, Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with R1.
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with LVT.
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Dual Port SRAM compiler.
Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Synchronous high density Dual Port SRAM memory compiler with input wrapper Mux.
Dual Port SRAM Compiler IP, UMC 0.11um SP process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous High-density Dual Port SRAM memory compiler.