UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
- UMC
- 90nm
- LL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm SP/RVT process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm SP/RVT process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm SP/RVT Low-K process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm SP/RVT Low-K process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process
USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process
USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Enhancement) Logic Process, without internal power clamping circuit
UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES
UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process.
2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process.
3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process
3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process
0.11um LVDS TX I/O PAD ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
0.11um LVDS TX I/O PAD ; UMC 0.11um HS/AE (AL Enhancement) Logic Process
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process
2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process
2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process