UMC L28HPC+ 28nm General Purpose PLL - 360MHz-1800MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
- UMC
- 28nm
- HPC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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UMC L28HPC+ 28nm General Purpose PLL - 360MHz-1800MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
TSMC CLN40ULPOD 40nm General Purpose PLL - 150MHz-750MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
TSMC CLN22ULPLVT 22nm General Purpose PLL - 350MHz-1750MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
TSMC CLN22ULP 22nm General Purpose PLL - 250MHz-1250MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
TSMC CLN12FFCLLLVT 12nm General Purpose PLL - 600MHz-3000MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
TSMC CLN12FFCLL 12nm General Purpose PLL - 400MHz-2000MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
GF L14LLP 14nm General Purpose PLL - 250MHz-1250MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
GF L12LLP 12nm General Purpose PLL - 250MHz-1250MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L28HPCLVT 28nm Deskew PLL - 220MHz-1100MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPCLVT 28nm Deskew PLL - 440MHz-2200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPCLVT 28nm Deskew PLL - 880MHz-4400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+LVT 28nm Deskew PLL - 225MHz-1125MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+LVT 28nm Deskew PLL - 450MHz-2250MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+LVT 28nm Deskew PLL - 900MHz-4500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+ 28nm Deskew PLL - 180MHz-900MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+ 28nm Deskew PLL - 360MHz-1800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+ 28nm Deskew PLL - 720MHz-3600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L110SP 110nm Deskew PLL - 59MHz-295MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L110SP 110nm Deskew PLL - 118MHz-590MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L110SP 110nm Deskew PLL - 236MHz-1180MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.