PCIe 5.0 PHY, SS 10LPP x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
- PCIe Gen5
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
PCIe 5.0 PHY, SS 10LPP x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, SS 10LPP x16, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, SS 10LPP x1, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, SMIC12SFe x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY,TSMC N5 x8, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, SF4X, x1, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b with AMBA bridge for CXL.io
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge + LTI and MSI-GIC interfaces
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
Adds security Interfaces, features to CXL 3.0 Premium controllers
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
112G PHY G2, TSMC N5 x4, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
32G PHY, TSMC N5 x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 32G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
32G PHY, TSMC N5 x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 32G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
32G PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 32G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
32G PHY, SS SF5A x2, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 32G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…