Verification IP for DisplayPort/eDP/DSC/DPI
A comprehensive VIP solution for DisplayPort (DP) and eDP source and sink designs.
Overview
A comprehensive VIP solution for DisplayPort (DP) and eDP source and sink designs. DP VIP implements a complete set of models, protocol checkers and compliance testsuites in 100% native SystemVerilog and UVM . Comprehensive support for DP/eDP source and sink design verification.
Specifications
|
Protocol Family |
Standard Organization |
Sub Protocol |
Models |
|---|---|---|---|
|
DP |
VESA |
DP 2.0.1 |
|
|
PICSIG |
PIPE 4.2 |
||
|
VESA |
VESA DisplayPort v1.4a Link Layer Compliance Test Specification(Link CTS) Revision 1.0 |
||
|
VESA |
VESA DisplayPort v1.4a PHY Layer Compliance Test Specification (PHY CTS) Revision 1. |
||
|
eDP |
VESA |
eDP 1.4b |
|
|
VESA |
VESA eDP Link Layer Compliance Test Guide v1.0 |
||
|
VESA |
VESA eDP Source PHY Compliance Test Guide v1.0 |
||
|
VESA |
HDCP 1.4/1.3, HDCP 2.3/2.2 |
||
|
CEA |
CEA-861-F |
||
|
DSC |
VESA |
DSC 1.2 |
|
|
DPI |
MIPI |
DPI-2 |
Key features
- Verification of transmitter/source, repeater and bridge and PHY designs
- SST, MSO and MST multi-stream transport
- AUX channel services
- Audio-audio and audio-video synchronization
- ALPM
- Supports I2C over AUX CH and EDID
- Supports DPCD registers
- PHY features include 1-4 lanes, inter-lane skew, receiver de-skew
- Adaptive sync
- Supports SSC
- Supports packing of all video RGB, YCBCR444,
- YCBCR422 and RAW color formats and frame rates
- HPD-based link training
- Supports HDCP 1.4, 2.2, 2.3 SST and MST
- Supports Display Stream Compression (DSC)
- Supports Display Parallel Interface (DPI) for pixel stream interface
- SPD and Main Stream Attribute (MSA) packets
- Comprehensive protocol checking and coverage report
- Functional traffic, error, and operational and power modes coverage
- Protocol analyzer tracker report at all layers
- Error injection and scoreboarding
- Native SystemVerilog UVM
- Standards-based and custom Avery Conformance test suites
- Verified with multiple IP vendor partners
What’s Included?
- Source, sink, repeater BFMs
- Compliance test suites
- User guide
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about Displayport IP core
VESA Adaptive-Sync V2 Operation in DisplayPort VIP
Understanding LTTPR: Enabling High-Speed DisplayPort Interconnects in Complex System Designs
DisplayPort 2025: Navigating the Next Wave of Display Innovation
Audio Transport in DisplayPort VIP
DisplayPort 2.1 vs DisplayPort 1.4: A Detailed Comparison of Key Features
Frequently asked questions about DisplayPort IP cores
What is Verification IP for DisplayPort/eDP/DSC/DPI?
Verification IP for DisplayPort/eDP/DSC/DPI is a Displayport IP core from Siemens Digital Industries Software listed on Semi IP Hub.
How should engineers evaluate this Displayport?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Displayport IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.