Vendor: Truechip Solutions Category: Displayport

eDP 2.0 Verification IP

The eDP 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of …

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Overview

The eDP 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of an ASIC/FPGA or SoC. The eDP VIP is fully compliant with the Standard eDP Version 2.0 specifications from VESA. This VIP is a lightweight VIP with an easy plug-and-play interface, so that there is no hit on the design time and the simulation time.

Key features

  • Fully compliant to VESA Embedded DisplayPort (eDP) Standard 2.0 Specification
  • Supports power saving feature:- Panel Self Refresh features PSR/PSR2, PR, Adaptive sync, and backlight control.
  • Supports HDCP version 1.4, 2.2 and 2.3
  • Supports Alternative Scrambler Seed Reset (ASSR)
    • TPS4 with ASSR is supported
  • Supports Advanced Link Power Management (ALPM)
    • Power Down states (Sleep and Standby)
    • Wake state (fast wake timing)
    • Supports updated ALPM requirement for DSC in eDP devices
  • Support RBR, HBR, HBR2, HBR3 (8b/10b) and UHBR10, UHBR13.5, UHBR20 (128b/132b) main link rates.
  • Supports 8b/10b and 128b/132b main link encoding.
  • Support ASSR with 128b/132b link encoding.
  • Supports 1, 2 and 4 lanes of operation on both eDP devices
  • Supports Aux Frame Sync for Active Video Timing Synchronisation
  • Supports GTC-based video timing synchronisation
  • Supports PSR (Panel Self Refresh) features
    • PSR Entry/Exit operation
    • Error Management/Recovery mechanism
  • Supports PSR2 operations
    • Self-refresh with selective updates supported
    • PSR2 States is supported
    • PSR2 commands and data transport are supported
  • Supports PSR SDP
  • Supports Multi-SST Operations (MSO)
    • Multi-SST Operation with Two SST Links, One Lane Each (2x1)
    • Multi-SST Operation with Two SST Links, Two Lanes Each (2x2)
    • Multi-SST Operation with Four SST Links, One Lane Each (4x1)
  • Supports DSC/FEC for 8b/10b and 128b/132b main link.
  • Supports Display Backlight Control via AUX
  • Support transport of Multi-touch data over AUX
  • Supports all operations of Main Link, Aux and HPD signalling
  • Support Link Training-Tunable PHY Repeaters (LTTPRs).
  • Callback support in BFM to provide user control
  • Supports Dynamic as well as Static Error Injection scenarios
  • Strong Protocol Monitor with real time exhaustive, programmable checks
  • Supports dynamically configurable modes
  • On-the-fly protocol checking using protocol check functions, static and dynamic assertions
  • Built in Coverage analysis.
  • Graphical analyzer to show transactions for easy debugging

Block Diagram

eDP 2.0 block diagram

Benefits

  • Available in native System Verilog (UVM/OVM/ VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity examples for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solutions and easy integration in IP and SoC environment

What’s Included?

  • DisplayPort eDP BFM's for:
    • Source - Link Layer
    • Source - MAC Layer
    • Source - PHY Layer
    • Sink - Link Layer
    • Sink - MAC Layer
    • Sink - PHY Layer
    • Branching Devices
  • DisplayPort layered monitor & scoreboard
  • Test Environment & Test Suite:
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
    • Compliance Test Suite
    • User Test Suite
  • Integration guide, user manual, and release notes
  • GUI analyzer to view simulation packet flow

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
eDP 2.0
Vendor
Truechip Solutions

Provider

Truechip Solutions
HQ: USA
Truechip is a leading provider of Design and Verification solutions – which help you to accelerate your design, lowering the cost and the risks associated in the development of your ASIC, FPGA and SoC. Truechip is a privately held company, with a global footprint and with a strong and experienced leadership team. Truechip was established in 2008 with a Mission to:
  • To create world class Verification IP Solutions
  • To provide expert consultancy to ASIC & SoC Design companies
  • To design SOCs from Architecture to Working Silicon
Our Vision is to:
  • To be the leading provider of Semiconductor IP Solutions
  • To be a one-stop-shop for Design and Verification
Our Guiding Principles are:
  • Customer Success
  • Commitment to Quality
    • Quality of Products
    • Quality of Engineers
  • Best in class Customer Support
  • Ethics and Integrity
We at Truechip leverage the extensive domain knowledge and expertise from current associations to provide complete set of design and verification solutions to our customers.
Contact Truechip Solutions

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Frequently asked questions about DisplayPort IP cores

What is eDP 2.0 Verification IP?

eDP 2.0 Verification IP is a Displayport IP core from Truechip Solutions listed on Semi IP Hub.

How should engineers evaluate this Displayport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Displayport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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