AHB Secure Subsystem - ARM Cortex M3
The Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software se…
AHB Performance Subsystem - ARM Cortex M0
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs n…
AHB Performance Subsystem - ARM Cortex M3
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs n…
AHB Low Power Subsystem - ARM Cortex M0
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SO…
APB I2C Master/Slave Controller
The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS.
AXI Performance Subsystem - ARM Cortex A
The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needin…
The I3C Controller Lite is a configurable I3C controller that can be used in microcontroller-based environments to provide I3C co…
The I3C Target is a configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to…
The I3C Autonomous Target is intended for simple, data acquisition types of applications where a microprocessor is not needed to …
The I3C Controller is a configurable I3C controller that can be used in microcontroller-based environments to provide I3C connect…
Ultra High-Speed Cache Memory Compiler - 2-Port Register File - TSMC N3P
The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an cache …
The DTS Adapter from Silvaco enables an existing IEEE 1149.1 debug test system (DTS) to take advantage of the debug/test capabili…
ColdFire V4 Processor delivering 500 DMIPS of performance
The ColdFire V2 Core & Standard Product Platform (CFV2SPPC1) combines the ColdFire V2 Core with industry-proven platform peripher…
ColdFire V2 IP Core low-gate count, high performance ColdFire architecture
The ColdFire V2 Core (CFV2CORE) is a small, yet implementation of the ColdFire architecture, offering over 250 DMIPS of performan…
The Real Time Clock (RTC) is a clock-calendar IP core that keeps track of the “Time of Day”.
APB to AHB-Lite Asynchronous Bridge
The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB Lite bus …
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the si…
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface.
The Encryption Standard (AES) IP Core is a hardware implementation encryption/decryption algorithm described in the U.S.