HDTV H.264/AVC Video Encoder with compressed reference frame store
The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm.
- Video Processing
- Proven in ASIC and FPGA
- Now
- ITU-T H.264 specification
HDTV H.264/AVC Video Encoder with compressed reference frame store
The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm.
Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder
The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm.
HDTV H.264/AVC Limited Baseline Video Decoder
The OL_H264LD core is a hardware implementation of the H.264 baseline video compression algorithm.
This core is a fully compliant implementation of the Message Digest Algorithm SHA-256.
This core is a fully compliant implementation of the Message Digest Algorithm MD5.
This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1.
This core family implements various aspects of the AES ( Encryption Standard) algorithm.
This core is a full implementation of the Triple DES encryption algorithm.
This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples.
QOI Image Decompressor IP Core
This core implements the QOI lossless image compression algorithm decompressing QOI header-less files and producing RGB 24 bits p…
This core implements the QOI lossless image compression algorithm producing a raw, header-less file.
Multi-channel HDTV H.264/AVC Encoder
The OL_H264e core is a hardware implementation of the H.264 video compression algorithm.
HDTV H.264/AVC Baseline Video Encoder
The OL_H264e core is a hardware implementation of the H.264 baseline video compression algorithm.