Xilinx UltraScale Plus NVME Hhost IP
The LDS NVME HOST ZUP IP is one of the most flexible NVME HOST IP in the market.
- NVMe Controller
- Good
- Now
- NVME 1.3
Xilinx UltraScale Plus NVME Hhost IP
The LDS NVME HOST ZUP IP is one of the most flexible NVME HOST IP in the market.
The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification.
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
Xilinx Ultra Scale NVME Host IP
The LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market.
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
Xilinx Ultra Scale Plus SATA HOST IP
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4…
Dual SATA Host controller on Virtex 5 FXT FPGA
The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
ZYNQ SATA 3 AHCI Host Controller with Linux Driver
The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a…
SATA 3 Host Controller on ZYNQ
The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA.
The LDS SATA RECORDER XV6 IP is a recorder system IP.
SATA III HOST Controller on Virtex 6
The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 …
Synchronous Universal Asynchronous Receiver/Transmitter
The macro MUART, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a micr…
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI sla…
The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus.
The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus.
The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus.
ARINC 429 Synchronous Transmitter Receiver
The M429T1R1 macro implements a synchronous single-chip ARINC 429 Transmit and Receive Controller Macro capable of linking one CP…
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master.