Stallable pipeline stage with width contraction
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with width expansion
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Stallable pipeline stage with protocol for multiway pipeline fork and join capability
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Application Adaptive Processor
A2P is a flexible processor architecture based on an “fine-grain” microarchitecture configurability and an expandable instruction…
The FIFO-CAM controls are designed to operate over a wide range of clock frequencies.
Half Precision IEEE-754R complete FPU for graphics processing
The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for…
Asynchronous FIFO with configurable flags and counts
The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports.
Synchronous FIFO with configurable flags and counts
The sFIFO controls are designed to operate over a wide range of clock frequencies.
Double & Single Precision IEEE-754 complete FPU
The A2FD is a fully synthesizable module implemented in Verilog RTL.
Very high performance IEEE-754 modules
The A2FM product is a collection of floating-point execution units compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for B…
Register, Configuration and Control Bus
A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, de…
Single Precision IEEE-754 complete FPU
The A2F is a fully synthesizable module implemented in Verilog RTL.
A2B is a high performance System-on-Chip interconnect designed for use in synthesizable designs.
Synchronous FIFO with second read/write port as companion to A2_CAM_FIFO
Synchronous FIFO with second read/write port as companion to A2_CAM_FIFO
The Queue Manager creates and maintains queues in memory for use in interprocess communication and I/O device communication with …