Vendor: SmartDV Technologies Category: VESA DSC

VDC-M Decoder IIP

VDC-M DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2.

Overview

VDC-M DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. VDC-M DECODER IIP is proven in FPGA environment. The host interface of the VDC-M DECODER can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

VDC-M Decoder IIP is supported natively in Verilog and VHDL

Key features

  • Supports VDC-M specification version 1.1 and 1.2.
  • Supports full VDC-M decoder functionality.
  • Supports following maximum bitrates (BPPmax), as follows:
    • 3 × bits_per_component,for 4:4:4
    • 2 × bits_per_component,for 4:2:2
    • 1.5 × bits_per_component,for 4:2:0
  • Supports any integer slice per line values
  • Supports any combination of bits_per_pixel and slice_width
  • Supports CSC(Color-space-conversion)
  • Supports the following Picture Hierarchy,
    • Block Level
    • Slice Level
    • Picture Level
  • Supports the following Per-mode Decoding Process ,
    • Transform Mode
    • BP Mode
    • MPP Mode
    • Fallback Modes
    • MPPF Mode
    • BP-SKIP Mode
  • Supports rate control (RC) algorithm in the determination of QP
  • Supports substream de-multiplexing
  • Supports Syntax parsing for Transform, BP, MPP, MPPF, and BP-SKIP modes
  • Supports following Hadamard transform applied in the YCoCg color space
    • 8-point Forward Hadamard Transform
    • 4-point Forward Hadamard Transform
  • Supports PPS decoding.

Block Diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The VDC-M DECODER interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
VDC-M Decoder IIP
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

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Frequently asked questions about VESA DSC IP cores

What is VDC-M Decoder IIP?

VDC-M Decoder IIP is a VESA DSC IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this VESA DSC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this VESA DSC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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