Ultra Ethernet Verification IP
The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet …
Overview
The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC. The UE VIP is compliant with IEEE standard 802.3-2018 & UE Specifications V1.0. This VIP is light weight with easy plug-and-play interface so that there is no hit on the design cycle time.
Key features
- Supports AI base profile.
- UET features: Message semantics, Packet delivery, tx congestion control sublayers
- PDS layer supports RUD, ROD and UUD PDS ordering modes.
- PDS supports single and multiple PDC establishment.
- SES supports relative and absolute addressing.
- PDS supports various error packets generation and reception.
- Supports SES-PDS logical interface
- Ethernet supports 100G, 200G, 400G, 800G and 1.6T as per IEEE Std 802.3.
- Supports Standard IP layer
- Supports Standard DLL layer
- Supports Standard ethernet PHY layer with 100G PHY lanes
- Callback support in all Layers to provide user control.
- Rich set of configurations and parameters.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking static and dynamic assertion.
- Built in Coverage analysis.
- Graphical analyzer to show transactions for easy debugging
Block Diagram
Benefits
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and coverage points with connectivity example for all the components
- Consistency of interface, installation, operation, and documentation across all our VIPs
- Provide complete solution and easy integration in IP and SoC environment
What’s Included?
- Deliverables Ultra Ethernet BFM’s for
- PDS layer with Congestion Management
- SES layer
- IP layer
- DLL Layer
- Reconciliation layer
- PCS layer
- PMA layer
- FEC layers (RS-FEC, BASE-R FEC)
- PMD layer
- Ethernet 100G/200G/400G/800G/1.6T layered monitors and scoreboard Test environment and Test Suite-
- Basic and Directed Protocol Tests
- Random Tests- Error Scenario Tests
- Assertions & Cover Point Tests
- User Test Suite
- Integration Guide, User Manual and Release Note
- GUI analyser to view simulation packet Flow
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
- To create world class Verification IP Solutions
- To provide expert consultancy to ASIC & SoC Design companies
- To design SOCs from Architecture to Working Silicon
- To be the leading provider of Semiconductor IP Solutions
- To be a one-stop-shop for Design and Verification
- Customer Success
- Commitment to Quality
- Quality of Products
- Quality of Engineers
- Best in class Customer Support
- Ethics and Integrity
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Frequently asked questions about Ethernet IP cores
What is Ultra Ethernet Verification IP?
Ultra Ethernet Verification IP is a Ethernet IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.