Vendor: Qualitas Semiconductor Category: UCIe

UCIe PHY (Die-to-Die) IP

The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …

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Overview

The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal Chiplet Interconnect Express™ (UCIe™) version 2.0 standard.

It supports both Standard and Advanced package types, offering the flexibility needed to build scalable, heterogeneous systems.
Designed for AI accelerators, data center SoCs, and custom multi-die architectures, this PHY IP delivers robust signal integrity and integration-ready support for next-generation chiplet-
based designs.

Key features

  • Compliant with UCIe v2.0, supporting 4/8/12/16/24/32GT/s data rates
  • for Standard Package up to 16 lanes / for Advanced Package up to 64 lanes
  • Provides a 1024-bit data bus width with high-throughput die-to-die communication
  • Includes automatic per-lane calibration and optional transmitter de-emphasis
  • Built-in Eye-Opening Monitor (EOM) and loopback test support for both internal and external testing
  • Supports subsystem optimization based on the customer’s chiplet architecture
  • Provides D2D-to-D2D SI/PI modeling and analysis, including full package and board considerations for customer-specific implementations

Block Diagram

UCIe PHY (Die-to-Die) block diagram

Specifications

Identity

Part Number
UCIe PHY (Die-to-Die)
Vendor
Qualitas Semiconductor
Type
Silicon IP

Files

Product Sheet Download

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Provider

Qualitas Semiconductor
HQ: South Korea
Qualitas Semiconductor is a leader in high-speed interconnect technology, which is at key infrastructure of the 4th Industrial Revolution, Encompassing AI, mobile devices, automotive systems, and displays. We specialize in high-speed interconnect circuit design, as well as ultra-fine semiconductor process design and verification. We operate our business through the licensing of high-speed interface IP and by providing comprehensive design services. Moreover, we have established a robust design methodology to ensure high-reliability in ultra-fine semiconductor processes. With a proven track record in developing and mass-producing cutting-edge semiconductors, our expertise spans the most advanced technologies.
Contact Qualitas Semiconductor

Learn more about UCIe IP core

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Cadence has successfully demonstrated first-pass silicon success of its UCIe™ standard package IP on Samsung Foundry's 5nm automotive process. This milestone underscores Cadence's commitment to delivering high-performance, automotive-grade IP solutions that meet the stringent requirements of next-generation automotive and high-performance computing applications.

40G UCIe IP Advantages for AI Applications

For AI workloads to be processed reliably at a fast rate, the die-to-die interface in multi-die designs must be robust, low latency, and most importantly high bandwidth. This article outlines the need for 40G UCIe IP in AI data center chips leveraging multi-die designs.

Frequently asked questions about UCIe IP cores

What is UCIe PHY (Die-to-Die) IP?

UCIe PHY (Die-to-Die) IP is a UCIe IP core from Qualitas Semiconductor listed on Semi IP Hub.

How should engineers evaluate this UCIe?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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