Vendor: SmartDV Technologies Category: SRAM

SRAM Memory Model

SRAM Memory Model provides an smart way to verify the SRAM component of a SOC or a ASIC.

Overview

SRAM Memory Model provides an smart way to verify the SRAM component of a SOC or a ASIC. The SmartDV's SRAM memory model is fully compliant with standard SRAM Specification and provides the following features. Better than Denali Memory Models.

SRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports SRAM memory devices from all leading vendors.
  • Supports 100% of SRAM protocol standard.
  • Supports all the SRAM commands as per the specs.
  • Supports Automated power down when deselected.
  • Supports write cycles operation.
  • Supports read cycles operation.
  • Supports complete static memory without clock and timing strobe.
  • Supports embedded error-correcting code for single bit error correction.
  • Supports equal address and chip enable access times.
  • Supports following device types,
    • X4
    • X8
    • X16
    • X32
  • Checks for following
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports full-timing as well as behavioral versions in one model.
  • Supports all timing delay ranges in one model: min, typical and max.
  • Protocol checker fully compliant with SRAM Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Constantly monitors SRAM behavior during simulation.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.
  • Supports the Windbond, Motorola, Cobham and Cypress part numbers CY7C199CN, CY7C1049DV33, CY62256N, CY62162G/CY62162GE, CY7C1062G/CY7C1062GE.

Block Diagram

Benefits

  • Faster testbench development and more complete verification of SRAM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the SRAM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
SRAM Memory Model
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

Learn more about SRAM IP core

Frequently asked questions about SRAM IP cores

What is SRAM Memory Model?

SRAM Memory Model is a SRAM IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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