Vendor: Cadence Design Systems, Inc. Category: USB

Simulation VIP for eUSB

The Verification IP (VIP) for eUSB is a VIP solution for the Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision …

Contact Provider Request Datasheet

Overview

The Verification IP (VIP) for eUSB is a complete VIP solution for the Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Revision 1.1. It provides a mature and comprehensive verification IP (VIP) for the eUSB protocol. Incorporating the latest protocol updates, the eUSB2 VIP is not only just a complete bus functional model (BFM) for the DUT operating in eUSB Native Mode but it also provides integrated automatic protocol checks and coverage model.

This VIP for eUSB provides support for any eUSB device in native mode: Host(eDSPn) or Device(eUSPn), in Repeater Mode: Host(eDSPr) or Device(eUSPr), Host Repeater, Peripheral Repeater and Hybrid Repeater. . It supports all eUSB operational speeds: Low, Full, or High. It provides multiple signaling eUSB interfaces: single-ended signaling for low-/full-speed mode and low-voltage differential signaling for high-speed mode to test and monitor all possible configurations of USB devices. The eUSB VIP is designed in such a way that it is easy for you to integrate in testbenches for IP, System-on-chip (SOC) and system level. The eUSB VIP helps you to reduce time to test by accelerate verification closure and ensure end product quality.

The VIP for USB runs on all major simulators and supports all main verification languages such as Verilog, System Verilog and e alongside with industry-standard methodologies for Testbench writing such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specifications: eUSB2 v1.1, USB2.

The following are the key features from the specifications that are implemented in the VIP:

Feature Name

Description

Supported DUT Types
  • All eUSB DUT types, such as in native mode: Host(eDSPn) or Device(eUSPn), in Repeater Mode: Host(eDSPr) or Device(eUSPr), Host Repeater, Peripheral Repeater, and Hybrid Repeater

Transaction Types
  • All types of transfers: bulk, control, interrupt, and isochronous transactions

Backward Compatible
  • Backward compatibility with USB 1.1 specifications

Enumeration
  • Provides a complete USB protocol hierarchy enumeration process for host and device models

Operational Speed
  • Operates at high, full, or low speed

Reset Signaling
  • Supports low/full-speed reset and high-speed chirp handshake

Suspend/Resume
  • Supports suspend, resume, remote wake-up, and low-power management (LPM)

Transaction and Packet Checks
  • Checks for all transaction and packet rules including inter-packet gap and propagation delays

Protocol Features in Repeater mode
  • Support for glitch handling
  • Support for variable SYNC bits handling
  • Support for first distorted SYNC bit handling
  • Support for dribble handling
  • Support for SE1 skew handling
  • Support for port reset in all states

Translator
  • Digital translator available for sending eUSB-compliant traffic

Register interface
  • Support to change the severity (Error, Warning, Info) of the protocol assertions
  • Support to initiate various commands such as reset, suspend/resume/remote wake-up, disconnect/connect, and so on
  • Support to control the functionality such as end-point buffers, chirp sequence, and clock frequency
  • Support to store information of the VIP model such as, device states, device address, end-point information, and other information that is easily accessible by the testbench
  • Support to insert error injections at the eUSB Phy
  • Support to initiate go to Port Reset from any state, issue silent and soft disconnect by device (eUSPn)

Predefined Error Injections
  • Device drives Port Reset during POR
  • Host drive ED+ as 1 instead of driving SE1 in Port Reset
  • Device corrupts the ACK in Port Configuration
  • Device drives invalid Connect Signal depending on the speed of operation
  • Device drives invalid ping
  • Host does not send an EOP
  • Host drives J signal instead of K during the resume operation
  • Host does not drive Resume signal after Remote wakeup from device
  • Host sends corrupted EOP to the device

Key features

  • Support testbench languages for SystemVerilog, UVM, OVM, and e
  • Runs on all major simulators
  • Generation of constraint-random bus traffic
  • Verify all device types: Host(eDSPn) or Device(eUSPn), Repeater Mode: Host(eDSPr) or Device(eUSPr), DUT as Hybrid Repeater.
  • Dynamic activation and reconfigure the VIP attributes anytime during the simulation
  • Built-in verification plan, protocol checks, and coverage model
  • Callback access at multiple TX and RX queue points for Scoreboard and data manipulation

Block Diagram

Simulation VIP for eUSB block diagram

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for eUSB
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

Learn more about USB IP core

What Designers Need to Know About USB Low-Power States

In addition to performance and interoperability, achieving low power has been one of the requirements for industry standards specifications. Some of the key specifications like Universal Serial Bus (USB), PCI Express (PCIe), and MIPI have defined power saving features for burst traffic. This whitepaper explains how Synopsys USB IP offers low power using various low power states that go beyond the basic features.

Frequently asked questions about USB IP cores

What is Simulation VIP for eUSB?

Simulation VIP for eUSB is a USB IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this USB?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP