USB4 VIP

The USB4 Verification IP (MX_USB4_VIP) provides a highly capable verification solution for the USB4 protocol which incorporating bus functional model (BFM), integrated protocol checkers and functional coverage along with assertion check. The USB4 VIP can be readily customized and optimized for a wide range of specific system application.

• Compliant with USB4 Specification.
• Supports USB3.2 Gen2 and Gen3 Operation.
• Support constrained randomization of protocol attributes.
• Support all types of error injection and detection.
• Support Dual lane.
• Support Side band channels as per USB4 specification.
• Configurable SERDES Interface width 32, 40, 64 and 80 bits.
• Support 64/66B Encoding and Decoding for Gen2.
• Support 128/132B Encoding and Decoding for Gen3.
• Support Scrambler and Descrambler.
• Support RS-Forward Error Correction (FEC).
• Support Clock compensation.
• Support Side band register space.
• Support Configuration register space.
• Support Lane adapter, Protocol adapter and Control adapter operations.
• Support Lane initialization process.
• Support Lane bonding mechanism.
• Support Error detection and Recovery mechanism.
• Support USB4 Link Equalization TxFFE handshake.
• Support all the Side Band Channel transactions.
• Support Sleep and Wake mechanism with respect to the tunneled protocols.
• Support Hot plug detection and Disconnect detection.
• Support Time Sync Notification Ordered Set (TSNOS).
• Support following Protocol tunneling,
  • USB3 tunneling
  • Display port tunneling
  • PCIE tunnelling
  • TBT3 (optional)
• Support all the Transport layer packets.
• Support HEC, ECC and CRC.
• Support Path Setup & Path Tear-Down mechanism.
• Support Flow control mechanism.
• Support all the Control packets.
• Support all the Notification events.

• Available in Pure System Verilog and with UVM methodology Support.
• Unique development methodology to ensure highest levels of quality.
• Availability of Compliance & Regression Test Suites.
• 24X5 customer support.
• Unique and customizable licensing models.
• Exhaustive set of assertions and coverage points with connectivity example for all the components.
• Consistency ofinterface, installation ,operation and documentation across all our VIPs.

• VIP user guide
• Complete documentation of all class, task , function etc used in verification env.
• USB4 VIP encrypted code
• Sample Testbench Top
• Built-in verification test plan includes-
• Basic Protocol Tests
• Random Tests
• Assertions & Coverage model