Vendor: Analog Bits Inc. Category: PLL

PCIe Gen4/5 Ref Clock SSCG PLL on GLOBALFOUNDRIES 12LP+

The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…

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GlobalFoundries 12nm LP View all specifications

Overview

The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Gen5 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments.

The PLL macro is implemented in Analog Bits’proprietary architecture that uses core and 1.8V IO devices.

With all components integrated, jitter performance and standby-power are significantly improved.

SSCG PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 24 25 MHz Input Frequency in Bypass Mode fBYPASS 100 MHz Output Frequency FOUT 5 100 2400 MHz Output Duty Cycle tDO 48 52 % Lock Time tLOCK 10 µs Reset Time tRESET 1 µs PLLOUT Random Jitter -- PCIe Gen4 RJPCIe4 0.5 ps-RMS PLLOUT Random Jitter -- PCIe Gen5 RJPCIe5 0.15 ps-RMS Modulation Frequency FM 30 33 kHz Modulation Depth (down-spread) DMD -5000 0 ppm Area A 0.12 sq. mm Total Power IDD 12 20 mW Standby Power IBG 0.5 1 mW Output Load CL 100 fF Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: SSCG PLL Operational Range

Key features

  • High performance design emphasis for meeting low jitter requirements in PCIe Gen4 & Gen5 applications
  • Implemented with Analog Bits’ proprietary LC architecture
  • Low power consumption
  • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • Excellent jitter performance with optimized noise rejection
  • Calibration code and Bandgap voltage observability (for debug)
  • Requires no additional on-chip components or band-gaps, minimizing power consumption

Files

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Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP —

Specifications

Identity

Part Number
PCIe Gen4/5 Ref Clock SSCG PLL on GLOBALFOUNDRIES 12LP+
Vendor
Analog Bits Inc.

Provider

Analog Bits Inc.
HQ: USA
Analog Bits develops, delivers and supports industry-leading, mixed signal IP solutions. The current product portfolio includes energy-efficient and low-area SERDES, PVT sensors, ultralow-jitter clocks, memory interfaces and I/O’s, available on every mainstream manufacturing process. Customers’ applications span a wide range including: high-volume consumer products, energy-efficient servers and advanced telecommunications equipment - all leveraging Analog Bits’ highly differentiated IP products. Founded in 1995, Analog Bits, Inc. has become the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Our products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized memories such as high-speed SRAMs and TCAMs. With billions of IP cores fabricated in customer silicon, from 0.35-micron to 14-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
Contact Analog Bits Inc.

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Frequently asked questions about PLL IP cores

What is PCIe Gen4/5 Ref Clock SSCG PLL on GLOBALFOUNDRIES 12LP+?

PCIe Gen4/5 Ref Clock SSCG PLL on GLOBALFOUNDRIES 12LP+ is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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