PCIe 7.0 PHY in TSMC (N5, N3P)

The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and chip-to-chip channels. The PHY’s unique DSP algorithms optimize analog to digital equalization and the patent-pending diagnostics features enable near zero link downtime. The PHY minimizes package crosstalk, allows dense SoC integration for x16 links, and achieves ultra-low-latency with an optimized data path that is based on an ADC architecture. Support for multiple standards form factors including OCP 3.0, U.2, and U.3 enables serve and storage applications. The PHY IP for PCIe 7.0, available in advanced FinFET processes including 3-nm and below, seamlessly interoperates with the Controller IP for PCIe 7.0 to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 128 GT/s PCIe 7.0 technology.

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 7.0, encoding, backchannel initialization
• Lane margining at the receiver
• Spread-spectrum clocking (SSC)
• PCIe power management features, including L0P, L1 substate; power gating and power island; DFE bypass option and
• voltage mode TX
• The multi-channel PHY macro with single clock and control core for higher density with support for both internal and external
• reference clock inputs
• PIPE bifurcation as well as PHY macro aggregation for up to 16-lane configurations
• Superior Rx jitter & cross talk tolerance reduces design constraints for a wider range of board layout designs
• Automated Test Equipment (ATE) test vectors for complete at-speed production testing
• Each PHY channel contains its own 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit sequencer (PRBS) for internal and external loopbacks
• Each channel is fully controllable via the integrated logic core as well as the test access port (TAP)

• Supports the latest features of PCIe® 7.0 specification
• Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
• Unique DSP algorithms deliver more power efficiency across channels
• Patent-pending diagnostic features enable near zero link downtime
• Minimizes package crosstalk with placement-aware architecture
• ADC/DSP based architecture for consistent performance across PVT variation
• Supports lane margining at the receiver
• Supports L0p substate power state
• Power gating and power island
• Embedded bit error rate tester (BERT) and internal eye monitor
• Built-in Self-Test vectors, pseudo random bit sequencer (PRBS) generation and checker
• Supports -40°C to 125°C junction temperatures
• Supports flip-chip packaging

• High-performance computing (HPC), storage area networks, networking switches, routers
• Artificial Intelligence (AI)

• Verilog models, Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl), GDSII, ATPG models IBIS-AMI models, Documentation