Vendor: Cadence Design Systems, Inc. Category: PCI Express

Simulation VIP for PIPE PHY

The Cadence® PIPE PHY Verification IP (VIP) provides a mature, capable verification solution for the PHY layer of complex protoco…

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Overview

The Cadence® PIPE PHY Verification IP (VIP) provides a mature, highly capable verification solution for the PHY layer of complex protocols such as PCIe 3/4/5, USB-3.x, USB-4, DisplayPort and SATA at the Intel PIPE (PHY Interface for PCI Express*, SAA, USB-3, DisplayPort, and Converged IO Architectures). The VIP supports simulation platform and enables metric-driven verification of IP and System on Chip (SoC) designs against PIPE PHY protocol specifications. PIPE PHY VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators.

Supported Specifications: Intel PIPE version 4.3, 4.4,1 and 5.2 specifications.

Key features

  • Device Type
    • PipeXceiver
    • SerialXceiver
    • PHYDUT Monitor
    • PHY Active VIP
  • PHY Architecture
    • Original PIPE architecture
    • SerDes Architecture
  • Pin Interface
    • Legacy Pin Interface
    • Low Pin Count Interface
  • Protocols Mode
    • USB 3.x
    • PCIe 3/4/5
    • USB4
  • Data Transmission Rate
    • USB 3.x: 5GT/s, 10GT/s
    • USB4: 10 GT/s. 20 GT/s, 10.3125 GT/s, 20.625 GT/s
    • PCIe: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s,32.0 GT/s
  • Clock Support
    • External Bit Clock
    • Internal Bit Clock (Recovery from Serial bit stream)
  • PCLK Modes
    • PCLK as PHY Input
    • PCLK as PHY Output
    • PCLK as both
  • LFPS
    • Supported
  • PIPE Data Width
    • 8/10, 16/20, 32/40 and 64/80 bit
  • Message Bus
    • M2P and P2M Transactions supported
    • All Message bus commands supported
    • Write Uncommitted
    • Write Committed
    • Read
    • Read Completion
    • Write ACK
  • Integrated Mode with Protocol VIP
    • USB3 , USB4, including Pipe
    • Phy Integrated Mode, is supported

Block Diagram

Simulation VIP for PIPE PHY block diagram

Files

Product Sheet Download

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Specifications

Identity

Part Number
Simulation VIP for PIPE PHY
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

Learn more about PCI Express IP core

Frequently asked questions about PCIe IP cores

What is Simulation VIP for PIPE PHY?

Simulation VIP for PIPE PHY is a PCI Express IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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