Vendor: Synopsys, Inc. Category: eFuse / OTP

NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)

Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in stand…

UMC 28nm HPC+ Available on request View all specifications

Overview

Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD process technologies with no additional masks or process steps. Small in area and low in power, Synopsys NVM IP delivers industry-leading reliability in products that support write cycle endurance from 1 to 1M times. Synopsys offers a broad portfolio of NVM, including one-time programmable (OTP), multi-time programmable (MTP), and few-time programmable (FTP) NVM
Validated through rigorous characterization, qualification, and reliability testing, the silicon proven NVM IP is delivered as a hard GDSII block and includes all the required control and support circuitry including the charge pump and high voltage circuits.
With more than a decade of development expertise, Synopsys offers the industry’s broadest portfolio of CMOS NVM IP with strong security, small area, fast access times, and high reliability for target applications in the automotive, industrial, and consumer markets.

Benefits

  • Broad portfolio of area-optimized reprogrammable CMOS NVM IP
  • Support for 64bits to 1Mbit configurations
  • 1 to 1M write cycle endurance
  • Standard CMOS and BCD processes with no additional masks or process steps
  • Up to 15+ years of data retention at 150°C
  • Integrated error checking and correction (ECC) functionality
  • Silicon characterized and qualified to exceed industry standards
  • Qualified for automotive AEC-Q100 Grade 0 and 1 temperatures in select process geometries

Applications

  • eFuse replacement
  • Analog trimming
  • Parameter setting
  • Security key storage
  • Code storage

What’s Included?

  • Databook
  • Production Test Flow document
  • Verilog behavior model
  • Abstract LEF and timing LIB files
  • GDSll layout database
  • CDL Netlist (OTP ONLY)

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC+ Available on request

Specifications

Identity

Part Number
dwc_nvm_otp_umc
Vendor
Synopsys, Inc.

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

Learn more about eFuse / OTP IP core

Why Hardware Root of Trust Needs Anti-Tampering Design

The hardware root of trust (HRoT) provides the trust base (root key), hardware identifier (UID), hardware unique key (HUK), and entropy required for the secure operation of the entire chip and therefore is often the focus of hacker attacks. If the design can’t effectively resist attacks, hackers can easily obtain the secrets of the entire chip. Attackers can use the secrets to crack identity authentication and data encryption and steal product design know-how, causing application security problems.

Optimizing Sensor Performance with 1T-OTP Trimming

A sensor is a device that detects a change in a stimulus and converts it into an electronic signal that can be measured or recorded. The stimulus can be many things, including a physical property, environmental parameter, chemical composition or a location, to name just a few. All sensing elements have nonlinearities that include an intrinsic nonlinearity over sensing range along with offset and sensitivity nonlinearity variations over temperature.

Solving Chip Security's Weakest Link

With the invention of Physical Unclonable Functions (PUF), we can now create a unique, inborn, unclonable key at the hardware level. The natural follow-up question to this is, “but how do we protect this key?” It is like storing your key to secrets in a drawer, a surefire way to break the secure boundary and create vulnerabilities.

Securing Smart Connected Homes with OTP NVM

The market for piracy is huge and hackers have become increasingly sophisticated even when security is implemented in hardware. The race between the aggressors and protectors is a battle without end. Smart connected home devices are increasingly storing and processing very sensitive and private user data in addition to attempting to deliver copyright protected content from service providers. Protecting consumer data is vital.

I-fuse: Most Reliable and Fully Testable OTP

Patented by Attopsemi™, I-fuse™ is a revolutionary non-breaking fuse technology that can be reliably programmed by heat assisted electromigration below a break point. Any cell can be tested as programmable if the initial fuse resistance is low enough (e.g. <400 ohms) to generate enough heat for programming.

Frequently asked questions about eFuse / OTP IP cores

What is NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)?

NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm) is a eFuse / OTP IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for umc Available on request.

How should engineers evaluate this eFuse / OTP?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this eFuse / OTP IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP