Vendor: Digital Core Design Category: I2C / I3C

MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification

The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus.

Overview

The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improvements in use and power, and performance. The Core uses just two pins and consumes a fraction of the energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced with a controller or application processor.

DCD maintains backward compatibility, enabling a smooth transition from I2C to I3C and simple implementation. The newest Core offers a flexible multi-drop interface between a host processor and peripheral sensors, to support the growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration, and supports low-power, high-speed, and other critical features that are currently covered by I2C and SPI.

Key features

  • Conforms to MIPI I3C v1.1 specifications
  • MIPI Manufacturer ID: 0x03B3
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
  • Legacy I2C messaging
  • I2C-like Single Data Rate messaging (SDR)
  • Master operation with FIFO:
    • Master transmitter
    • Master receiver
  • Supports flexible transmission speed modes:
    • FAST-PLUS (up to 1000 kb/s)
    • SDR (up to 12,5 Mb/s)
  • Configurable FIFO size up to 256 Bytes
  • Configurable SDA/SCL glitch filter
  • Software programmable SDA/SCL bus timings
  • Multi-master systems supported
  • Interrupt generation
  • Allows operation from a wide range of input clock
  • frequencies (build-in 12-bit clock timer)
  • Configurable interface allows easy connection to standard
  • bus interfaces: APB, AHB, 8051, 80251, others
  • Support for in-band interrupts
  • Support for I3C common command codes
  • Dynamic address assignment (DAA) support
  • Command queue support
  • Low power management support
  • Fully interoperable with third-party I3C master and slave
  • solutions
  • Fully synthesizable, static synchronous design with
  • positive edge clocking and synchronous reset
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

Applications

  • Smartphones, tablets and laptops,
  • IoT
  • Medical, health & fitness,
  • Autonomous vehicles and ADAS,
  • Embedded microprocessor boards,
  • Low-power applications,
  • Communication systems etc

What’s Included?

  • HDL Source Code
  • Testbench environment
    • Automatic Simulation macros
    • Tests with reference responses
  • Synthesis scripts
  • Technical documentation
  • 12 months of technical support

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
DI3CM-HCI
Vendor
Digital Core Design
Type
Silicon IP

Provider

Digital Core Design
HQ: Poland
Founded in 1999, Digital Core Design is a global leader in IP core development, specializing in microprocessor, microcontroller, and communication solutions. With a portfolio of over 100 IP cores, DCD continues to drive innovation in embedded systems, providing cutting-edge solutions for automotive, industrial, IoT, and security applications.

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Frequently asked questions about I2C / I3C IP cores

What is MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification?

MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification is a I2C / I3C IP core from Digital Core Design listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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