I2C Slave
The I²C slave IP is fully synthesizable core and compatible with Phillips I²C standard.
Overview
The I²C slave IP is fully synthesizable core and compatible with Phillips I²C standard. The IP uses I²C Bus Protocol which helps maximize the hardware efficiency and minimize the interfaces.
The I²C Slave IP Core is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.
Key features
- Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
- Uses two wires to transfer information between devices
- Bi-directional data transfer
- 7-bit addressing format
- Fixed data width of 8 bits
- Data transfer in multiples of bytes
- Interrupt or bit-polling driven byte-by-byte data transfer
- Start/Stop detection
- Operates from a wide range of input clock frequency
- Fully synthesizable
Block Diagram
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about I2C / I3C IP core
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MIPI CCI over I3C: Faster Camera Control for SoC Architects
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Frequently asked questions about I2C / I3C IP cores
What is I2C Slave?
I2C Slave is a I2C / I3C IP core from System Level Solutions, Inc. listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.