Vendor: Silicon Library Inc. Category: Multi-Protocol PHY

MIPI DPHY & LVDS Transmit Combo on GF55LPe

This MIPI DPHY/LVDS Combo Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications and LVDS specifications.

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GlobalFoundries 55nm LPe View all specifications

Overview

This MIPI DPHY/LVDS Combo Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications and LVDS specifications. This IP supports up to 1.5Gbps for both MIPI and LVDS data rate. This IP can be applied to OpenLDI v0.95 also. This IP includes two PLLs. One is a generic PLL for MIPI clock generation, and the other is an X8/X7 multiplier PLL for serial clock generation.

Key features

  • MIPI D-PHY version 1.2 compliant PHY transmitter
  • OpenLDI version 0.9 compliant LVDS transmitter
  • Consists of 6 lanes configurable to be 4+1 MIPI and 7 lanes LVDS
  • Supports HS mode (80Mbps to 1.5Gbps) and LS mode (up to 10Mbps) for MIPI mode
  • Support up to 1.5Gbps LVDS with 7:1 serializer
  • Integrated control interface logic to supports PHY Protocol Interface (PPI)
  • Configurable analog characteristics
    • Differential voltage
    • Common mode voltage
    • PLL divider/loop filter
  • Support at-speed loopback BIST
  • 2.5V/1.2V power supply
  • Support GlobalFoundry 55nm LPe process

Block Diagram

SLIPMPTDCMG55LE block diagram

What’s Included?

  • Verilog RTL or netlist source code of lane control unit
  • Liberty timing models for synthesis and STA
  • Timing constrains for synthesis and physical layout
  • Verilog behavior model of PHY part
  • Physical design database
  • Integration guidelines

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 55nm LPe —

Specifications

Identity

Part Number
SLIPMPTDCMG55LE
Vendor
Silicon Library Inc.
Type
Silicon IP

Provider

Silicon Library Inc.
HQ: Japan
Silicon Library Inc. (SLI) is a leading provider of high speed interface semiconductor IP and IC solutions. SLI's product offerings included silicon-proven/production-proven eDP/DP TX and RX IP, HDMI TX and RX IP, . SLI offers one-stop shop of both Link and PHY as optimally designed solution. In order to maintain the highest IP quality, SLI staffs its own test team and equipments to verify the IP implementation in actual silicon.
Contact Silicon Library Inc.

Learn more about Multi-Protocol PHY IP core

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The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is MIPI DPHY & LVDS Transmit Combo on GF55LPe?

MIPI DPHY & LVDS Transmit Combo on GF55LPe is a Multi-Protocol PHY IP core from Silicon Library Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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