32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps.
- TSMC
- 28nm
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps.
your custom Switch Fabric, AI, or HPC ASIC with Credo’s SerDes IP.
Ultra-short reach SerDes with 500 Gbit/s throughput
The Glasswing SerDes family is a set of programmable IPs designed and optimized for in-package applications.
Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detail…
MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
The MIPI D-PHY Analog TX IP Core adheres fully to version 1.2 of the D-PHY specification.
Sensor / Display MIPI A-PHY Source IP
The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking ap…
Sensor/Display MIPI A-PHY Sink IP
The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking ap…
ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash c…
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in SMIC 65/55SP
The single-port IP core, HDMI receiver PHY (Physical layer), completely complies with HDMI 1.4's specifications.
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in SMIC 40LL
IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY provides a…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in SMIC 65/55SP
IP core that completely conforms with HDMI 1.4 requirements for physical layer HDMI transmitters For consumer electronics like DV…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 65/55ULP
IP core that completely conforms with HDMI 1.4 requirements for physical layer HDMI transmitters For consumer electronics like DV…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY provides a…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
IP core that completely conforms with HDMI 1.4 requirements for physical layer HDMI transmitters For consumer electronics like DV…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 90/85G
Physical layer IP core for HDMI transmitters that adheres to HDMI 1.4 requirements in full For consumer electronics like DVD play…
HDMI 2.1 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The HDMI V2.1 Rx complies with version 2.1 of the HDMI specification and offers a full single-link HDMI receiver function.
HDMI 2.1 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The HDMI V2.1 Tx complies with version 2.1 of the HDMI specification and offers a full single-link HDMI transmitter capability.
DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps …
DDR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+)
The DDR4/3 PHY is compatible with JEDEC DDR3 and JEDEC DDR4 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to 2133Mbps…
DDR4/ DDR3/ DDR3L Combo PHY IP - 1600Mpbs (Silicon Proven in TSMC 28HPC+)
This DDR (Double Data Rate) PHY IP supports DDR3/DDR3L/DDR4, provides low latency, and enables up to 1600Mbps throughput.