How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Mobiveil Inc.
Category:
DDR
Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
The UMMC (Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2) is a flexible and c…
Overview
The UMMC (Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2) is a highly flexible and configurable design that supports RLDRAM2, RLDRAM3 and JEDEC compliant DDR5, DDR4 3DS, DDR4, DDR3, LPDDR3, LPDDR3 and LPDDR2 memories. It is targeted for high bandwidth access and low power consumption such as next-generation mobile, networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.
Features
- Supports multiple ranks
- Supports 16/8/4 banks per rank
- Configurable AXI address width
- Configurable Request queue depth
- Configurable Write and Read data FIFO size
- Configurable QoS through various arbitration schemes
- Supports following MC Clock to PHY Clock ratio - 1:1 (Full-rate Mode), 1:2 (Half-rate Mode), 1:4 (Quarter rate Mode)
- Supports self-refresh and partial array self-refresh
- Supports Auto-refresh, per-bank refresh and multi-bank refresh (RLDRAM)
- Supports various power down modes - Active/Precharge/Deep power down
- Supports Intelligent request scheduling
- Maximizes bus efficiency through look-ahead command processing and bank-level parallelism
Design Attributes
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Software control for key features
Key features
- Compliant with AXI4 specification
- Compliant with DFI 3.1/ 5.1 Specification
- RLDRAM2/RLDRAM3 support and JEDEC compliant DDR3/DDR4/DDR5/LPDDR2/LPDDR3 support
- Supports memory data width from 8 to 64 bits for DDR3, DDR4, DDR5, LPDDR2 & LPDDR3 and x9, x18, x36 devices in any combined data width for RLDRAM2 & RLDRAM3
- Supports chip select interleaving
- Supports single and multi-port host buses AMBA4 AXI upto 32 ports
Block Diagram
DDR5_4_3 block diagram
What’s Included?
- Product Package
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Documentation
- Design Guide
- Verification Guide
- Synthesis Guide
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
DDR5_4_3
Vendor
Mobiveil Inc.
Provider
Mobiveil Inc.
HQ:
USA
Mobiveil is a fast-growing Technology company that specializes in creation of Intellectual Properties, Application Platforms and solutions for Flash Storage, wired and wireless communications, IoT, Industrial and Robotics
The Mobiveil team leverages decades of experience in delivering high-quality, production-proven, high-speed serial interconnect Silicon IP cores to the leading customers worldwide. With a highly motivated engineering team, dedicated integration support, flexible business models, strong industry presence through strategic alliances and key partnerships, Mobiveil solutions have added tremendous value to the customers in executing their marketing and engineering goals within budget and on time.
Mobiveil is headquartered in the Silicon Valley with engineering development centers located in Milpitas, CA, Chennai, Bangalore, Hyderabad and Rajkot India, and sales offices and representatives located in US, Europe, Israel, Japan, Taiwan and People Republic of China.
If you are interested in choosing Mobiveil as your IP partner and would like to understand what's unique about our IP offerings, receive our whitepaper - "What it takes to deliver a configurable and quality Silicon IP." To get your copy write to us at ip@mobiveil.com (We recommend you use your corporate email address please)
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
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This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
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Frequently asked questions about DDR Controller IP cores
What is Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2?
Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2 is a DDR IP core from Mobiveil Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.