How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Truechip Solutions
Category:
DDR
DDR6 Verification IP
The DDR6 Verification IP provides an effective & efficient way to verify the components interfacing with DDR6 interface of an ASI…
Overview
The DDR6 Verification IP provides an effective & efficient way to verify the components interfacing with DDR6 interface of an ASIC/FPGA or SoC. The DDR6 VIP is fully compliant with Standard DDR6 specification from JEDEC. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.
Key features
- Supports connection to any DDR6 Memory Controller IP communicating with a JEDEC compliant DDR6 Memory Model.
- Supports configurable SDRAM addressing of different sizes(x4,x8 and x16).
- Available in all memory sizes from upto 128 Gb.
- Supports UDIMM,RDIMM, LRDIMM Memory configurations.
- Supports 3DS in all DIMM Configurations with command-to-command timings checks in SLR & DLR
- Supports Data Masking(DM).
- Supports Cyclic Redundancy Check (CRC)
- Support for all speed-grades/speed-bins.
- Supports Programmable burst lengths.
- Supports configurable timing parameters and rank associations.
- Supports capturing all the valid DDR6 commands including Activate,Read Write, Precharge.
- Supports Power-up Reset and initialization sequences.
- Supports Precharge Power-Down, Active Power-Down, Self-Refresh operation.
- Reports various timing errors, which can be used to check any timing violations.
- Provides full control to the user to enable/disable various types of messages.
- Supports full timing models or bus functional models.
- Support for Multiple Ranks & Quad channel architecture.
- Supports advanced SystemVerilog features like constrained random testing.
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using protocol check functions, static and dynamic assertion.
- Built in Coverage analysis.
- Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
- Graphical analyzer to show transactions for easy debugging
Block Diagram
DDR6 Verification IP block diagram
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- 24X5 customer support & response under 90 minutes.
- Unique and customizable licensing models.
- Exhaustive set of assertions and cover points with connectivity example for all the components.
- Consistency of interface, installation, operation and documentation across all our VIPs.
- Provide a complete solution and easy integration in IP and SoC environment
What’s Included?
-
eliverables
- DDR6-SDRAM Model
- DDR6 Monitor & Scoreboard
- DDR6 Memory Controller BFM/Agent
- DDR6 PHY BFM model
- DDR6 Phy Monitor and Scoreboard
- Test-Bench Configurations
- Test Suite (Available in Source code)
- Basic Protocol Tests
- Directed & Random Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
DDR6 Verification IP
Vendor
Truechip Solutions
Provider
Truechip Solutions
HQ:
USA
Truechip is a leading provider of Design and Verification solutions – which help you to accelerate your design, lowering the cost and the risks associated in the development of your ASIC, FPGA and SoC.
Truechip is a privately held company, with a global footprint and with a strong and experienced leadership team.
Truechip was established in 2008 with a Mission to:
- To create world class Verification IP Solutions
- To provide expert consultancy to ASIC & SoC Design companies
- To design SOCs from Architecture to Working Silicon
- To be the leading provider of Semiconductor IP Solutions
- To be a one-stop-shop for Design and Verification
- Customer Success
- Commitment to Quality
- Quality of Products
- Quality of Engineers
- Best in class Customer Support
- Ethics and Integrity
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
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Frequently asked questions about DDR Controller IP cores
What is DDR6 Verification IP?
DDR6 Verification IP is a DDR IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.