Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library Generic Core Cell Library.
- UMC
- 65nm
- LL
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 8 tracks, UMC 65nm LL process
UMC 65nm LL-HVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm SP process
UMC 65nm SP/RVT process Core Cell Library mini Library.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Mini-Library Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 8 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process
UMC 0.13um LL FSG Logic process Enhanced Mini-Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um HS/FSG process
UMC 0.13um HS process Generic Core Cell Library (enhanced Mini-Library).
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG process enhanced Mini-Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG process high density Core Cell Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Enhanced Mini-Library Standard Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um LL/FSG process
UMC 0.11um LL/FSG Logic process high density Generic Core Cell Library.
Standard Cell (ECO) Library IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Metal1 Start ECO Core Cell Library (for FSR0H_M).
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process high density Core Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um SP/FSG process
UMC 0.11um SP/FSG process mini-lib Core Cell Library.
Standard Cell (MiniLib) Library IP, UMC 0.11um HS/AE process
UMC 0.11um AL/HS Logic process Mini-Library standard Cell Library.
Standard Cell (MiniLib) Library IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AL Logic process high density Cell Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Advance Enhancement) Logic process Mini-Library Cell Library.
Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 90nm LL process
UMC 90nm LL-LVT Generic Core Cell Library.
Standard Cell (Generic) Library IP, LVT, 10 tracks, UMC 90nm SP process
UMC 90nm SP/LVT Low-K process Utral high speed Cell Library.
Standard Cell (Generic) Library IP, RVT, RTC Cell, UMC 90nm LL process
UMC 90nm LL/RVT Low-K Logic process 3.3V RTC Cell Library.