Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library.
- UMC
- 90nm
- LL
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process
UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version).
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process
UMC 65nm SP/HVT process POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm LL process
UMC 65nm LL/HVT Low-K Logic process POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library POWERSLASHKit.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K process POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 12-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 12-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 7-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, LVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 8-Track POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 12-Track high speed POWERSLASH Cell Library (C40).