UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 40nm LP with power gating & peri-HVT 1PRF
- UMC
- 40nm
- LP
Register File IP cores provide reusable on-chip storage structures for processors, controllers, and accelerators in modern SoC and ASIC designs.
These IP cores support small, high-speed storage structures used in processors, DSPs, and accelerators, helping designers balance density, speed, power, and reliability in memory-centric subsystems
This catalog allows you to compare Register File IP cores from leading vendors based on density, performance, power efficiency, and process node compatibility.
Whether you are designing CPU cores, DSP engines, AI accelerators, or custom datapaths, you can find the right Register File IP for your application.
UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm EFLASH Process Two Port Register File
UMC 55nm EFLASH Process Two Port Register File
UMC 55nm eFlash peocess One Port Register File memory compiler_x005F_x000D_
UMC 55nm eFlash peocess One Port Register File memory compiler
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.
UMC 0.18UM Mixed Mode/RF; Two Port Register File
UMC 0.18UM Mixed Mode/RF; Two Port Register File
UMC 0.18UM Mixed Mode/RF; One Port Register File Memory Compiler
UMC 0.18UM Mixed Mode/RF; One Port Register File Memory Compiler
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT
One Port Register File Compiler IP, UMC 28nm HPC process
UMC 28nm HPC process One Port Register File
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm SP Logic Low-K process synchronous Two Port (1R1W) Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process PG Two Port Register File compiler.