UMC L28HPC+ 28nm Multi Phase DLL - 360MHz-1800MHz
The Multi Phase DLL is designed for high-speed interface applications.
- UMC
- 28nm
- HPC
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
UMC L28HPC+ 28nm Multi Phase DLL - 360MHz-1800MHz
The Multi Phase DLL is designed for high-speed interface applications.
UMC L28HPC+ 28nm Multi Phase DLL - 720MHz-3600MHz
The Multi Phase DLL is designed for high-speed interface applications.
UMC L28HPC+ 28nm IoT PLL - 60MHz-900MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power.
UMC L28HPC 28nm IoT PLL - 60MHz-875MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power.
UMC L28HPCLVT 28nm General Purpose PLL - 440MHz-2200MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L28HPC+LVT 28nm General Purpose PLL - 450MHz-2250MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L28HPC+ 28nm General Purpose PLL - 360MHz-1800MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L28HPCLVT 28nm Deskew PLL - 220MHz-1100MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPCLVT 28nm Deskew PLL - 440MHz-2200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPCLVT 28nm Deskew PLL - 880MHz-4400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+LVT 28nm Deskew PLL - 225MHz-1125MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+LVT 28nm Deskew PLL - 450MHz-2250MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+LVT 28nm Deskew PLL - 900MHz-4500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+ 28nm Deskew PLL - 180MHz-900MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+ 28nm Deskew PLL - 360MHz-1800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L28HPC+ 28nm Deskew PLL - 720MHz-3600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L110SP 110nm Deskew PLL - 59MHz-295MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L110SP 110nm Deskew PLL - 118MHz-590MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L110SP 110nm Deskew PLL - 236MHz-1180MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L110LL 110nm Deskew PLL - 30MHz-150MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.