Clocking and timing IP cores are fundamental to semiconductor designs that require accurate clock generation, distribution, synchronization, and timing control. This category includes PLLs, DLLs, oscillators, and clock generators used in SoCs, ASICs, SerDes subsystems, processors, memory interfaces, and communication devices.
Browse clocking and timing IP from multiple vendors to compare jitter, frequency range, locking behavior, power consumption, programmability, and process support. Semi IP Hub helps chip architects and design engineers identify the right timing IP for high-performance and low-power silicon platforms.
PLL (Frequency Synthesizer) IP, Input: 25/50MHz, Output: 400MHz, UMC 90nm SP process
Input 25/50MHz, output 400MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K process.
PLL IP, Input: 10MHz - 200MHz, Outout: 50MHz - 1000MHz, UMC 90nm SP process
This Phase-Locked Loop (PLL) based clock multiplier.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm LL process
Input 20M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 90nm low leakage (RVT) Low-K process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 100MHz, Output: 20MHz - 300MHz, UMC 90nm SP process
Input 5M-100MHz, output 20M-300MHz, fractional-N frequency synthesizable PLL, UMC 90nm SP/RVT Logic Low-K process.
Input 200M-400MHz, output 800M-1600M 400-800MHz and 200-400MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 50MHz, Output: 667MHz - 1300MHz, UMC 90nm SP process
Input 25M-50MHz, output 667M-1300MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL IP, Input: 32.768KHz, Output: 12MHz - 30MHz, UMC 90nm SP process
Input 32.768KHz, output 12M-30MHz, PLL, UMC 90nm SP/RVT Logic Low-K process.
PLL (Frequency Synthesizer) IP, Input: 156.25MHz, Output: 625MHz, UMC 90nm SP process
Input 156.25MHz, output 625MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 90nm LL process
Input 20M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT Low-K Logic process.
Input 10M-500MHz, Output 31.25M-500MHz, frequency synthesizer PLL, UMC 65nm SP/RVT Low-K process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 65nm LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 65nm LL/RVT process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 65nm LP process
Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 65nm LP/RVT Low-K Logic process.
PLL (Mini-PLL) IP, Input: 20MHz - 200MHz, Output: 31.5MHz - 500MHz, UMC 65nm SP process
miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 31.5MHz and 500MHz, UMC 65nm SP/RVT Low-K Logic…
Input 25-33.33MHz, output 600MHz/800MHz, 400MHz/533MHz, 200MHz/266MHz frequency synthesizable PLL, UMC 65nm SP/RVT Low-K Logic pr…
PLL (Frequency Synthesizer) IP, Input: 1MHz - 5MHz, Output: 15MHz - 600MHz, UMC 65nm LL process
Input 1M-5MHz, output 15M-600MHz, frequency synthesizable PLL, UMC 65nm LL/RVT Low-K process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm SP process
Input 20M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low-K Logic process.
Input 200M-400MHz, output 800M-1600M, 400-800MHz and 200-400MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low-K Logic process.
Input 33.33M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low-K process.
Input 33M-300MHz, output 1000M-1500MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low-K process.
Input 12MHz, output 800MHz/1000MHz, 533MHz/666MHz, 400MHz/500MHz, 266MHz/533MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low…