Clocking and timing IP cores are fundamental to semiconductor designs that require accurate clock generation, distribution, synchronization, and timing control. This category includes PLLs, DLLs, oscillators, and clock generators used in SoCs, ASICs, SerDes subsystems, processors, memory interfaces, and communication devices.
Browse clocking and timing IP from multiple vendors to compare jitter, frequency range, locking behavior, power consumption, programmability, and process support. Semi IP Hub helps chip architects and design engineers identify the right timing IP for high-performance and low-power silicon platforms.
UMC L40G 40nm Spread Spectrum PLL - 150MHz-750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
UMC L40G 40nm Spread Spectrum PLL - 300MHz-1500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
UMC L40G 40nm Spread Spectrum PLL - 600MHz-3000MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreadin…
UMC L65LP 65nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L65LL 65nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L65SP 65nm General Purpose PLL - 260MHz-1300MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L55LP 55nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L55SP 55nm General Purpose PLL - 260MHz-1300MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L40LP 40nm General Purpose PLL - 150MHz-750MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L40G 40nm General Purpose PLL - 340MHz-1700MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability.
UMC L65LP 65nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L65LP 65nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L65LP 65nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L55LP 55nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L55LP 55nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L55LP 55nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L40LP 40nm Deskew PLL - 75MHz-375MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L40LP 40nm Deskew PLL - 150MHz-750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L40LP 40nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
UMC L40G 40nm Deskew PLL - 170MHz-850MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.