WebM’s G2 VP9 Decoder IP is the latest addition to WebM family of hardware IP products for multimedia system-on-chip designs.
- TSMC
- 28nm
- Silicon Proven
Graphics and vision IP cores enable advanced image processing, video handling, and visual computing in modern SoC and ASIC designs.
These IP cores are used in a wide range of applications including mobile devices, automotive systems, surveillance, industrial vision, and AI-powered imaging.
This catalog allows you to explore and compare graphics and vision IP cores from leading vendors based on performance, power efficiency, resolution support, and process node compatibility.
Whether you are developing computer vision systems, multimedia applications, or AI imaging pipelines, you can find the right IP to optimize your design.
WebM’s G2 VP9 Decoder IP is the latest addition to WebM family of hardware IP products for multimedia system-on-chip designs.
Accelerates AI and Hyperscale Data Center Applications The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach…
112G-ELR PAM4 SerDes PHY - TSMC 5nm
112G-ELR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channels…
224G-LR SerDes PHY enables 1.6T and 800G networks
The ever-increasing bandwidth in high-performance computing (HPC) applications is driving the rapid growth of high-speed I/O capa…
The 56G Long-Reach (LR) SerDes PHY provides exceptional performance with best-in-class power and area, making it ideal for machin…
112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
In data center interconnects, short-reach connectivity is needed in use-case scenarios for chip-to-chip, chip-to-optical-module, …
Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES Receiver on TSMC CLN65LP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN28HPL
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Chip-to-Chip IO Buffer on TSMC CLN6FF
The Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
Chip-to-Chip IO Buffer on TSMC CLN5A
The Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
Chip-to-Chip IO Buffer on TSMC CLN5
The Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
Chip-to-Chip IO Buffer on TSMC CLN4P
The Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…
The Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, usi…