Foundation Library IP cores provide the fundamental building blocks required for ASIC and SoC implementation, enabling efficient digital design, physical synthesis, timing closure, and manufacturing across advanced semiconductor process nodes.
This category includes both Standard Cell Libraries and I/O Pad Libraries, covering logic cells, sequential elements, low-power cells, level shifters, ESD-protected I/O interfaces, and process-specific implementation libraries optimized for leading foundries.
This catalog enables semiconductor engineers to evaluate and compare Foundation Library IP solutions from multiple vendors based on process node support, PPA (Power, Performance, Area) characteristics, library characterization quality, voltage domains, reliability requirements, and integration with modern EDA design flows.
Whether targeting AI accelerators, automotive SoCs, networking devices, wireless chipsets, or high-performance computing applications, engineers can identify the Foundation Library IP best suited to their technology, performance, and manufacturing requirements.
40nm Low Leakage VHS, Channel Length 40nm, ULVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, ULVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, power managerment kit, RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, engineering change order, RVT Logic Process Standard cell Library
40nm Low Leakage VHS, Channel Length 40nm, PEK, ULVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, PEK, ULVT Logic Process Standard cell Library
40nm Low Leakage VHS, Channel Length 40nm, PEK, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, PEK, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, engineering change order, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, HVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, engineering change order, HVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 50nm, RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 50nm, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 50nm, HVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, RVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, PMK,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, PMK,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, HVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,RVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,LVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,HVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,HVT Logic Process Standard cell Library