Foundation Library IP cores provide the fundamental building blocks required for ASIC and SoC implementation, enabling efficient digital design, physical synthesis, timing closure, and manufacturing across advanced semiconductor process nodes.
This category includes both Standard Cell Libraries and I/O Pad Libraries, covering logic cells, sequential elements, low-power cells, level shifters, ESD-protected I/O interfaces, and process-specific implementation libraries optimized for leading foundries.
This catalog enables semiconductor engineers to evaluate and compare Foundation Library IP solutions from multiple vendors based on process node support, PPA (Power, Performance, Area) characteristics, library characterization quality, voltage domains, reliability requirements, and integration with modern EDA design flows.
Whether targeting AI accelerators, automotive SoCs, networking devices, wireless chipsets, or high-performance computing applications, engineers can identify the Foundation Library IP best suited to their technology, performance, and manufacturing requirements.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60).
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60).
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60).
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90).
UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)
UMC 28nm HPM/RVT Logic Process 12-track generic cell library with LPLUS (C38)
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library
UMC 28nm HPM/LVT Logic Process 12-track eco_m1_core library
UMC 28nm HPM/LVT Logic Process 12-track eco_m1_core library
UMC 28nm HPM/HVT Logic Process 12-track eco_m1_core library (C35)
UMC 28nm HPM/HVT Logic Process 12-track eco_m1_core library (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
UMC 55nm eFlash/RVT Logic Process High Speed 12-track ECO_M1 cell library
UMC 55nm eFlash/RVT Logic Process High Speed 12-track ECO_M1 cell library
UMC 55nm eFlash/HVT Logic Process High Speed 12-track ECO_M1 cell library
UMC 55nm eFlash/HVT Logic Process High Speed 12-track ECO_M1 cell library
UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library
UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Frequency OSC IO Cell Library
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Frequency OSC IO Cell Library
UMC 55nm ULP LowK Logic Process Ture 3.3V high Frequency OSC IO Cell Library
UMC 55nm ULP LowK Logic Process Ture 3.3V high Frequency OSC IO Cell Library
UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library
UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library
UMC 0.11um HS/AE (AL Enhancement) Logic Process BOAC Multi-voltage IO with Power-on Tri-state/Low Function.