Vendor: Qualitas Semiconductor Category: Single-Protocol PHY

Ethernet PHY IP

The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.

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Overview

The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces. Supporting data rates up to 64Gbps per lane, it is optimized for next-generation Ethernet, PCIe, and custom high-speed links in AI accelerators, networking switches, and chiplet-based SoCs.With support for PAM4 and NRZ signaling, advanced equalization, and scalable lane architecture, this IP ensures robust signal integrity across long-reach and high-loss channels.

Key features

  • Compliant to 802.3 Ethernet specification - 200GBASE-KR4, 200GBASE-CR4, 100GBASE-KR4, 100GBASE-CR4, 100GBASE-KR2, 100GBASE-CR2, 50GBASE-KR, 50GBASE-CR, 40GBASE-KR4, 40GBASE-CR4, 25GBASE-KR, 25GBASE-CR, 10GBASE-KR, 10GBASE-CR
  • Data rate supported - Ethernet: NRZ 3.125 - 26.5625Gb/s, PAM4 53.125Gb/s
  • DSP-based architecture using high-performance ADC/DAC for RX/TX
  • Lane configurations: X1, X2 or X4
  • PCS in soft-macro and PMA in hard-macro
  • Reed / Solomon Forward Error Correction(RS FEC)
  • MCU and firmware-driven Link Training(LT)/Auto Negotiation(AN) delivers flexible functionality and tuning.
  • RX eye-opening monitor
  • Loopback feature capable of generating and checking PRBS patterns

Block Diagram

Ethernet PHY IP block diagram

Files

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Specifications

Identity

Part Number
Ethernet PHY IP
Vendor
Qualitas Semiconductor
Type
Silicon IP

Provider

Qualitas Semiconductor
HQ: South Korea
Qualitas Semiconductor is a leader in high-speed interconnect technology, which is at key infrastructure of the 4th Industrial Revolution, Encompassing AI, mobile devices, automotive systems, and displays. We specialize in high-speed interconnect circuit design, as well as ultra-fine semiconductor process design and verification. We operate our business through the licensing of high-speed interface IP and by providing comprehensive design services. Moreover, we have established a robust design methodology to ensure high-reliability in ultra-fine semiconductor processes. With a proven track record in developing and mass-producing cutting-edge semiconductors, our expertise spans the most advanced technologies.
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Learn more about Single-Protocol PHY IP core

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Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is Ethernet PHY IP?

Ethernet PHY IP is a Single-Protocol PHY IP core from Qualitas Semiconductor listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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