The USB Super-Speed+ PHY IP is a compact and power-efficient interface solution that fully supports the USB 3.2 Gen1 and Gen2 spe…
- Single-Protocol PHY
The USB Super-Speed+ PHY IP is a compact and power-efficient interface solution that fully supports the USB 3.2 Gen1 and Gen2 spe…
The SLVS-EC RX PHY IP is a high-speed, low-power receiver macro compliant with SLVS-EC v3.0 specification, enabling reliable para…
The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.
The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …
The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
The PCIe Gen4.0 PHY IP offers a low-power, compact solution with proven performance and robust signal and power integrity, making…
DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards.
CSI-2 RX IP supports both C-PHY v1.2 and D-PHY v2.0 interfaces, enabling flexible integration across a wide range of image sensor…
The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
The DSC Encoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
The PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with glob…
The DP and eDP TX/RX PHY IP provides a compact, low-power solution for high-speed external display interfaces.
The C/D-PHY Combo IP delivers top-tier PPA characteristics and is mass production-proven across multiple customer SoCs.
The Intra-panel TX PHY IP is a low-power transmitter designed for COG (Chip-on-Glass) and COF (Chip-on-Film) display modules.
20G MSS (Multi-standard SerDes) PHY
20G MSS (Multi-standard SerDes) PHY