Single Port SRAM Compiler IP, UMC 0.35um SP process
UMC 0.35um Logic process synchronous high speed Single Port SRAM memory compiler.
- SRAM
SRAM IP cores provide reusable on-chip storage structures for processors, controllers, and accelerators in modern SoC and ASIC designs.
These IP cores support fast on-chip volatile storage for caches, buffers, and tightly coupled memories, helping designers balance density, speed, power, and reliability in memory-centric subsystems
This catalog allows you to compare SRAM IP cores from leading vendors based on density, performance, power efficiency, and process node compatibility.
Whether you are designing processors, accelerators, embedded SoCs, or high-speed control systems, you can find the right SRAM IP for your application.
Single Port SRAM Compiler IP, UMC 0.35um SP process
UMC 0.35um Logic process synchronous high speed Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process high density, Low Power mini Single Port SRAM.
Dual Port SRAM Compiler IP, UMC 0.153um MS process
UMC 153nm Mixed-Mode/Logic process synchronous high density Dual Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.162um G2 process
UMC 0.162um GII Logic process synchronous high density Single Port SRAM memory compiler.
AHB system Peripheral IP, SRAM controller, Soft IP
Static memory controller with AHB interface.