One Port Register File Compiler IP, UMC 0.13um CIS process
UMC 130nm CMOS Image SensorCu process One Port Register File compiler.
- UMC
- 130nm
- HS
Register File IP cores provide reusable on-chip storage structures for processors, controllers, and accelerators in modern SoC and ASIC designs.
These IP cores support small, high-speed storage structures used in processors, DSPs, and accelerators, helping designers balance density, speed, power, and reliability in memory-centric subsystems
This catalog allows you to compare Register File IP cores from leading vendors based on density, performance, power efficiency, and process node compatibility.
Whether you are designing CPU cores, DSP engines, AI accelerators, or custom datapaths, you can find the right Register File IP for your application.
One Port Register File Compiler IP, UMC 0.13um CIS process
UMC 130nm CMOS Image SensorCu process One Port Register File compiler.
One Port Register File Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE Logic process Synchronous One Port Register File memory compiler with 1.41um2-Bit cell.
One Port Register File Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash process One Port Register File.
One Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process 1.41um2 cell Single Port Register File (One Port Register File) memory compiler.
One Port Register File Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um AE eFlash HS process for One Port Register File compiler.
One Port Register File Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Enhancement) Logic process 1.41um2 cell One Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous Two Port SRAM memory compiler.
Two Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous high density Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 65nm SP process
UMC 0.65um SP/RVT Low-K Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process synchronous high density Two Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous Single Port SRAM.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low_K Logic process synchronous high density One Port Register File compiler.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process synchronous Low Power (PG-DC) using 0.425-Bit cell Single Port Register File memory compiler.
One Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process Low Power synchronous high density One Port Register File compiler.
One Port Register File Compiler IP, UMC 0.13um CIS process
UMC 0.13um 2P4M 1.5V CMOS Image Sensor process synchronous Single Port Register File SRAM compiler.
One Port Register File Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous high density Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process standard asynchronous high density Single Port Register File SRAM memory compiler.