UMC 28nm HPC process Two Port Register File with LVT and Bank2
UMC 28nm HPC process Two Port Register File with LVT and Bank2
- UMC
- 28nm
- HPC
Register File IP cores provide reusable on-chip storage structures for processors, controllers, and accelerators in modern SoC and ASIC designs.
These IP cores support small, high-speed storage structures used in processors, DSPs, and accelerators, helping designers balance density, speed, power, and reliability in memory-centric subsystems
This catalog allows you to compare Register File IP cores from leading vendors based on density, performance, power efficiency, and process node compatibility.
Whether you are designing CPU cores, DSP engines, AI accelerators, or custom datapaths, you can find the right Register File IP for your application.
UMC 28nm HPC process Two Port Register File with LVT and Bank2
UMC 28nm HPC process Two Port Register File with LVT and Bank2
UMC 28nm HPC process Two Port Register File with peri LVT
UMC 28nm HPC process Two Port Register File with peri LVT
UMC 28nm HPC process Two Port Register File with Bank2
UMC 28nm HPC process Two Port Register File with Bank2
UMC 28nm HPC process 2PRF with Bank2
UMC 28nm HPC process 2PRF with Bank2
UMC 28nm HPC process Two Port Register File
UMC 28nm HPC process Two Port Register File
UMC 40nm uLP process ULL One Port Register File memory compiler
UMC 40nm uLP process ULL One Port Register File memory compiler
UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT
UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT
40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature
40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature
UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.
UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm EFLASH Process Two Port Register File
UMC 55nm EFLASH Process Two Port Register File
UMC 55nm eFlash peocess One Port Register File memory compiler_x005F_x000D_
UMC 55nm eFlash peocess One Port Register File memory compiler