Display Stream Compression (DSC 1.2) Encoder

The Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel input using either RGB or YCbCr in 4:4:4 or 4:2:2 format. The DSC Encoder core integrates industry standard interfaces for host configuration and control, video input, and output.

Host

32-bit AMBA Peripheral Bus 4 (APB) slave interface for programming and control. All internal configuration and status registers are accessible from the slave APB interface.

Input

Parallel streaming interface with VSync and HsSync support for image framing.

Output

AXI4-Stream Protocol interface is implemented to support the transfer of encoded data.

Performance & Area

The DSC Encoder implementation includes best-in-class design processes and is efficient in resource usage and operating frequency. The core requires less than 250K gates in the TSMC 28HP process, and a 175MHz core clock performs 4K encode. For detailed information on area and timing, please contact Trilinear Technologies with the specific technology platform required.

• Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications
• Low gate count and low latency implementation
• Three clock domains
  • Stream and APB clocks operate the applicable interfaces
  • Independent decoder clock runs the core functions
• Fully compliant with the VESA DSC 1.2 standard
• Uses synchronous design techniques and a technology abstraction layer for internal SRAM buffers
• Allows for migration from FPGA or FPGA prototype to ASIC with no functional changes to the core
• Completely pipelined; can be stalled as necessary to properly manage input and output rates