Display Stream Compression (DSC 1.2) Decoder

The Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions from 480 to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel using either RGB or YCbCr in 4:4:4 or 4:2:2 format. The DSC Decoder core integrates industry standard interfaces for host configuration and control, data input, and video output.

Host

32-bit AMBA Peripheral Bus 4 (APB) slave interface for programming and control. All internal configuration and status registers are accessible from the APB interface.

Input

AXI4-Stream Protocol interface supports the transfer of encoded data to the core at 2 or 4 bytes per clock cycle.

Output

Parallel streaming interface with end-of line and top-of-frame indicators.

Performance & Area

The DSC Decoder implementation includes best-in-class design processes and is efficient in resource usage and operating frequency. The core requires less than 300K gates in the TSMC 28HP process, and a 175MHz core clock performs 4K decode. For detailed information on area and timing, please contact Trilinear Technologies with the specific technology platform required.

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• Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications
• Low gate count and low latency implementation
• Three clock domains:
  • Stream and APB clocks operate the applicable interfaces
  • Independent decoder clock runs the core functions
• Fully compliant with the VESA DSC 1.2a standard
• Uses synchronus design techniques and a technology abstraction layer for internal SRAM buffers
• Allows for migration from FPGA or FPGA prototype to ASIC with no functional changes to the core
• Completely pipelined; can be stalled as necessary to properly manage input and output rates

• HDL source files for the function design
• HDL source files for block level and top level testing
• Functional specification
• Timing constraints summary document
• Generic SRAM simulation models
• C Reference Driver