Learn more about Standard Cell Libraries IP core
Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use.
The free lunch offered for decades by Moore’s law is now over and scaling down to the next technology node no longer offers the required energy efficiency gains. Design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the demands of the new IoT markets.
This article suggests an innovative approach to build an optimal PMNet per application requirements, based on the definition of four standardized voltage levels (further defined as Interfaces for the Distribution of Power). Finally, it demonstrates the advantages of this approach from which regulator suppliers or designers, SoC integrators and system makers can benefit.
Assessing the comparative performances of several Standard Cell Libraries in a reliable way is a tricky project as it deals with statistical issues. The objective of this paper is dual. The first objective is to demonstrate that the « cell-by-cell » approach to compare libraries is inconsistent with actual performances results obtained after P&R of libraries on a logic circuit. The second objective is to present benchmarks and methods to compare efficiently and reliably different libraries with different architectures (e.g. CCSL versus RCSL).
Using pulsed latches instead of flip-flops is a solution that has been thoroughly studied for its advantages in speed, density, and power consumption reduction [1] [2]. Even so, this solution has not been widely adopted by standard cell library providers because of the difficulties related to timing verifications: pulse width integrity and hold time closure. There is also a lack of EDA tools natively supporting this feature. Dolphin Integration delivers standard cell libraries based on pulsed latches (SESAME uHD libraries) that can be used in standard design flows and fully compatible with the most common EDA tools.
This paper showcases the study on the Setup/Hold inter-dependence. It examines different existing methods for characterization and presents a new method to determine the Setup/Hold pairing for Standard Cells. This new method developed by Dolphin Integration is applied particularly on the pulsed latch (spinner system) in order to obtain the best compromise between circuit's speed and the reliability.
