6 track Ultra High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 LeFP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latc…
Overview
Key features
- Ultra High-Density
- 7% up to 15% denser after P&R than standard 7-Track library
- Hand tuned cells, designed with 6-Track for optimal area reduction
- Pulsed latches as ?Spinner Cells? instead of flip-flops: for min. 30% gain in density
- Metal 1 power rails
- With smooth implementation
- Pulse generation automated by the script for ?Insert pulse generation?
- Spinner cell design minimizing hold time violations
- Ideal for slow to medium speed logic blocks
- Flexibility and ease of integration
- Multi VTs (SVT, LVT and HVT MOS versions) to deliver optimal performance, power and area results
- Support of CCS timing and power
- Complete set of PVT corners including temperature inversion corners, multi VDD characterization, custom PVT support
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 55nm | GP | Pre-Silicon |
Specifications
Identity
Provider
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Frequently asked questions about standard cell libraries
What is 6 track Ultra High Density standard cell library at TSMC 55 nm?
6 track Ultra High Density standard cell library at TSMC 55 nm is a Standard Cell Libraries IP core from Dolphin Semiconductor listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.
How should engineers evaluate this Standard Cell Libraries?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Standard Cell Libraries IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.