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PCIe 4.0 Controller

Overview

The PCIe 4.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express® (PCIe®) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.1/3.0. A PCIe 4.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

How the PCIe 4.0 Controller works

The PCIe 4.0 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 4.0 and 3.1/3.0 specifications, as well as the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

Key Features

  • PCI Express layer
    • Comprises complete PCIe 4.0 interface subsystem with Rambus PCIe 4.0 PHY
    • Compliant with the PCI Express 4.0 and 3.1/3.0, and PIPE (8-, 16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
    • Supports x16, x8, x4, x2, x1 at 16 GT/s, 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, and other optional features
    • Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
  • User Interface layer
    • 256-bit transmit/receive low-latency user interface
    • User-selectable Transaction/Application Layer clock frequency
    • Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
    • Optional Transaction Layer bypass

Benefits

  • 20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 6400 customers , including several hundred of ASIC tape-outs
  • Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL.
  • Availability for PCIe 4.0 early adopters
  • Silicon target 16 nm FinFET TSMC and 28 nm roadmap
  • Integrated in ongoing projects with multiple 16G PHY
  • Root-port, Endpoint, Dual-mode, Switch in depth flexible configuration
  • Support for advanced Low Power states enables lower power consumption in energy-conscious applications
  • Configurable user interface with clock-domain-crossing provides maximum interfacing flexibility and throughput.
  • Extensive data integrity features provide data protection on entire data path for storage and other data critical applications
  • Acclaimed global 24/5 support

Block Diagram

PCIe 4.0 Controller Block Diagram

Applications

  • HPC,
  • Cloud Computing,
  • AI,
  • Machine Learning,
  • Enterprise,
  • Networking,
  • Automotive,
  • AR/VR,
  • Test and Measurement

Deliverables

  • Verilog RTL,
  • Supporting Documentation

Technical Specifications

Foundry, Node
Any
Maturity
In production
Availability
Available
Request Info

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