Vendor: Rambus, Inc. Category: PCI Express

PCIe 4.0 Controller

The PCIe 4.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express® (PCIe®) 4.0 performance with great desi…

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Overview

The PCIe 4.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express® (PCIe®) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.1/3.0. A PCIe 4.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

How the PCIe 4.0 Controller works

The PCIe 4.0 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 4.0 and 3.1/3.0 specifications, as well as the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

Key features

  • PCI Express layer
    • Comprises complete PCIe 4.0 interface subsystem with Rambus PCIe 4.0 PHY
    • Compliant with the PCI Express 4.0 and 3.1/3.0, and PIPE (8-, 16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
    • Supports x16, x8, x4, x2, x1 at 16 GT/s, 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, and other optional features
    • Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
  • User Interface layer
    • 256-bit transmit/receive low-latency user interface
    • User-selectable Transaction/Application Layer clock frequency
    • Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
    • Optional Transaction Layer bypass

Block Diagram

PCIe 4.0 Controller block diagram

Benefits

  • 20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 6400 customers , including several hundred of ASIC tape-outs
  • Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL.
  • Availability for PCIe 4.0 early adopters
  • Silicon target 16 nm FinFET TSMC and 28 nm roadmap
  • Integrated in ongoing projects with multiple 16G PHY
  • Root-port, Endpoint, Dual-mode, Switch in depth flexible configuration
  • Support for advanced Low Power states enables lower power consumption in energy-conscious applications
  • Configurable user interface with clock-domain-crossing provides maximum interfacing flexibility and throughput.
  • Extensive data integrity features provide data protection on entire data path for storage and other data critical applications
  • Acclaimed global 24/5 support

Applications

  • HPC,
  • Cloud Computing,
  • AI,
  • Machine Learning,
  • Enterprise,
  • Networking,
  • Automotive,
  • AR/VR,
  • Test and Measurement

What’s Included?

  • Verilog RTL,
  • Supporting Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
PCIe 4.0 Controller
Vendor
Rambus, Inc.

Provider

Rambus, Inc.
HQ: USA
Rambus delivers industry-leading chips and silicon IP for the data center and AI infrastructure. With over three decades of advanced semiconductor experience, our products and technologies address the critical bottlenecks between memory and processing to accelerate data-intensive workloads. By enabling greater bandwidth, efficiency and security across next-generation computing platforms, we make data faster and safer.
Contact Rambus, Inc.

Learn more about PCI Express IP core

Challenges in PCI Express IP Implementation

IP selection, verification and integration are key aspects to the success of an IP-based design. This paper describes some of the challenges imposed by an IP based implementation of the technology and discusses about possible solutions to address them.

Realizing the Performance Potential of a PCI-Express IP

This paper describes challenges involved in realizing the maximum performance of a configurable interconnect IP (GPEX - Rambus PCI Express Digital Controller). The following sections describe how various performance metrics such as roundtrip latency and bandwidth can be used to characterize a PCI Express IP performance and its impact on the system. The ideas presented can also be applied to other high speed interconnect architectures like RapidIO and Hypertransport

Frequently asked questions about PCIe IP cores

What is PCIe 4.0 Controller?

PCIe 4.0 Controller is a PCI Express IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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