Crest factor reduction (CFR) selectively reduces the peak-to-average ratio (PAR) of wideband digital signals, such as those used in third-generation (3G) code division multiple access (CDMA) or long term evolution (LTE) wireless applications.
The Lattice peak cancellation crest factor reduction (PC-CFR) IP core is part of the digital front end (DFE) suite of IP cores optimized for HetNet applications. The core is highly programmable and can be customized to achieve the desired resource vs performance trade off. The core is optimized for use with ECP3 FPGA family and achieves up to 4dB of PAR reduction for LTE signals.
Crest Factor Reduction IP
Overview
Key Features
- The Lattice PC-CFR IP supports between 1 to 4 antennas
- The core can be configured for clock-to-sample ratios of 1, 2 or 4
- Provides 1, 2 or 3 sequential detection and cancellation stages to remove peaks
- Cancellation pulses may be real or complex
- Pulse coefficients can be pre-configured at generation time through coefficient file or configured during operation through the Wishbone interface
- Each filter stage can be independently configured with detection target peak threshold and cancellation pulse coefficients
- Number of clip engines for each filter stage can be independently configured
- The maximum cancellation pulse length is configurable.
- The IP provides parallel or TDM (Time-Division Multiplexing) quadrature (I & Q) format for input/output mode
- Configurable data width
- Configurable coefficient width
- Option for input/output gain
Block Diagram
