Adaptive Voltage Scaling (AVS) Bus Target IP

The MAXVY's AVS Bus Slave IP is a highly configurable IP that provides full AVS Bus slave functionality compliant with the AVS Bus specification. The IP enables seamless communication between an AVS Bus Master, such as a processor, FPGA, or SoC, and AVS Bus-compliant target devices used in power management applications.

Designed for both FPGA and ASIC implementations, the MAXVY's AVS Bus Slave IP supports both 2-wire and 3-wire AVS Bus communication modes, providing flexibility for integration with a wide range of AVS Bus-based systems. The IP can operate as an AVS Bus target device, receiving commands from an AVS Bus master and generating protocol-compliant responses.

The architecture consists of an optional Processor Interface for configuration, status monitoring, and register access. The processor interface can be implemented using AXI4-Lite, APB, AHB-Lite, Wishbone, or a custom register interface based on system requirements. A dedicated Synchronization Module ensures reliable clock-domain crossing between the processor interface and the AVS Bus domain.

The AVS Target subsystem incorporates a Command Decoder that receives and interprets incoming AVS Bus command frames, a Response Generator that creates protocol-compliant acknowledgment and status response frames, and a CRC Checker that performs cyclic redundancy check verification to ensure data integrity and robust error detection. Together, these blocks enable reliable command processing and communication with the AVS Bus master.

The IP supports protocol error handling, status reporting, interrupt generation, clock resynchronization, and timeout detection, making it suitable for Dynamic Voltage and Frequency Scaling (DVFS), power management, industrial, automotive, networking, and high-performance computing applications.

• Full AVS Bus Slave (Target) functionality.
• Supports both 2-wire and 3-wire AVS Bus interfaces.
• Optional Processor Interface with AXI4-Lite, APB, AHB-Lite, Wishbone, or custom interface.
• Synchronization module for clock-domain crossing.
• Command Decoder for AVS Bus command processing.
• Response Generator for acknowledgment and status frame generation.
• Integrated CRC Checker for error detection and frame validation.
• Supports slave status response frames.
• Positive-edge clocked architecture.

• AVS Bus-Compliant Voltage Regulator Control
• Dynamic Voltage Scaling (DVS)
• Dynamic Voltage and Frequency Scaling (DVFS)
• Processor Core Voltage Management
• FPGA Core Voltage Control
• Power Supply Monitoring and Status Reporting
• Fault Detection and Protection Reporting
• Intelligent Power Delivery Systems
• Adaptive Power Management Solutions

• Verilog Source code
• User Guide
• IP Integration Guide
• Simulation Script
• Synthesis Script
• Encrypted UVM Verification Environment
• Basic Testsuite
• Firmware code