Vendor: Advanced Architectures Category: FIFO / CAM

Asynchronous FIFO with configurable flags and counts

The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports.

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Overview

The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports. Only single control lines are re-synchronized between the two clock domains ensuring hazard free operation. The requirement for Gray coded addressing is thus eliminated. A wide range of clock frequencies and relative frequencies between read and write ports are fully tolerated. The interface signals are fully synchronous to their respective domains; no asynchronous signals are present on either side. Only reset may be asynchronous in that it is asserted asynchronously and synchronized internally to both clock domains to again ensure hazard free operation.

Key features

  • Fully Synthesizable RTL - Verilog
  • Static Timing Analysis compatible
  • Dual-port inferred RAM architecture
  • Configurable width and depth 
  • Standard FIFO handshake interface 
  • Insensitive to relative clockrates
  • Flags or depth values on each port

Block Diagram

A2_aFIFO block diagram

Applications

  • Re-synchronizing data between clock domains
  • General purpose buffering

Specifications

Identity

Part Number
A2_aFIFO
Vendor
Advanced Architectures
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Advanced Architectures
HQ: USA
Advanced Architectures is a service operation searching for successful partnerships and satisfied customers. It is already working with industry leaders, mid-size and small-size companies. A2's staff consists of experienced engineering personnel. Their scope of product exposure makes them unique compared to single product environments. The extent of the services available makes A2 very valuable to start-up, emerging growth companies and to emerging divisions in large companies. Advanced Architectures has extensive knowledge and experience in the development and application of high performance computing systems. Designs have ranged from complete supercomputer designs to customized DSP solutions with microprocessor based control and custom compute engines for compression and decompression algorithms
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Frequently asked questions about FIFO / CAM IP cores

What is Asynchronous FIFO with configurable flags and counts?

Asynchronous FIFO with configurable flags and counts is a FIFO / CAM IP core from Advanced Architectures listed on Semi IP Hub.

How should engineers evaluate this FIFO / CAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FIFO / CAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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