Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process
Vrr=2.2V, Vfr=2.0V, A type IO, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.
- UMC
- 110nm
- HS
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process
Vrr=2.2V, Vfr=2.0V, A type IO, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process
Vrr=2.2V, Vfr=2.0V, A type IO, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Power on Reset IP, Input: 2.5V, UMC 40nm LP process
Vrr=2.0V Vfr=1.9V, VCC3I=2.5V, 2.5V Power On Reset, special request, UMC 40nm LP/RVT Low-K Logic process.
Power on Reset IP, Input: 2.5V, UMC 40nm LP process
2.5V Power On Reset, Vrr=1.90 without Vfr, UMC 40nm LP/RVT Low-K Logic process.
Power on Reset IP, Input: 1.0V/3.3V, UMC 40nm LP process
Vrr=2.33V Vfr=2.26V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset, special request, UMC 40nm LP/RVT Low-K Logic process.
PLL (Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/FSG process
5GHz SSCG with 25MHz reference clock, UMC 0.11um 20T HS/FSG Logic process.
PLL (Spread Spectrum) IP, 20MHz - 70MHz, UMC 0.18um G2 process
UMC 0.18um GII Logic process 20MHz-70MHz delay-type spread-spectrum clock generator.
Input clock range:10M ~ 1280MHz, output clock range:15.625M ~ 2000MHz wide-range SSCG, UMC 0.11um HS/AE (AL Enhancement) 2T Logic…
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
Input 80M-150MHz, output 80M-150MHz, frequency synthesizable PLL, UMC 0.13um Logic EHS/FSG process.
PLL (Frequency Synthesizer) IP, Input: 66MHz - 100MHz, Output: 400MHz - 800MHz, UMC 90nm SP process
Input 66M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 90nm SP Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 55nm LP process
Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 40nm LP process
Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 28nm HPM process
Input 25-66MHz, output 400-800MHz, frequency synthesizable PLL, UMC 28nm HPM Logic process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.11um HS/FSG Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 40nm LP process
Input 20M-200MHz, output 500M-1GHz, frequency synthesizable PLL, UMC 40nm LP/RVT Low-K Logic process.
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequenc…